Gate-all-around (GAA) nanowire channel field-effect transistors (FETs) enable feature scaling beyond current planar complementary-metal-oxide semiconductor (CMOS) technology. In its basic form, a nanowire-based FET includes a source region, a drain region and nanowire channels between the source and drain regions. A gate which surrounds the nanowire channels regulates electron flow through the nanowire channels between the source and drain regions.
Feature size scaling, however, poses a challenge for today's high performance, high-power electronic devices. Take as an example, battery-powered mobile devices such as laptop computers. Without power management provisions in place, normal computing operations would quickly deplete power stores.
Many power management strategies exist at the chip level, such as powering down non-active blocks or reducing supply voltage (Vdd) during a “sleep mode.” However, most of these approaches involve design overhead in terms of either managing the power-down and/or designing the circuits robustly so that they will maintain state at a lowered Vdd, where compact models typically have poor accuracy. As a result, conventional devices will almost always incur higher design and production costs to ensure the circuits function at lower Vdd. These costs arise both from checking the design itself over a wider range of voltages, as well as ensuring that the device produced is well calibrated across this range of Vdd's. Plus, there is also the risk that if these tasks are not performed correctly, the costs associated with a re-design cycle might also be incurred.
Therefore, scalable nanowire-based FET designs that permit power consumption regulation would be desirable.